Washington State University Vancouver uses Cadence software and is a Cadence University Program Member.
The Cadence components are as follows
IC design tools or IC610 version IC18.104.22.1680.7
Cadence and Synopsys CAD tools expose the students to the complete design process of building complex, ready to fabricate integrated circuits. The design framework enables the student to design and simulate circuits using device models that are customized for specific foundries, create layout based on process specific design rules and also provide tools for complete verification of the design as well as overall chip assembly.
Specifically the tools under the Cadence Design Framework integrate a variety of design activities including:
- Schematic capture
- Analog circuit simulation: The schematics can be simulated using functional level using Verilog simulation tools or a accurate analog simulator such as Spectre
- Layout design
- Design Rule checking
- Layout versus schematic checking and verification
- Standard cell generation
Specific components of the Cadence-Synopsys tools perform specific tasks and collectively provide a design flow that can be used to design, simulate, layout, verify a industrial strength state of the art IC design. Additionally there are tools that allow the place and route of standard cells as well as Verilog synthesis with the RTL compiler tool.
This information was last updated on 6/14/2016.
Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134